We identify problems in the design stage and propose optimization through verification of signal integrity including analysis of electric parameters to ensure matching of characteristic impedance, modeling of connector components, and coordinated design including LSI packages or chips.
Transient analysis / AC analysis
Transient analysis for whole systems
We conduct transient analysis of the whole systems, which allows us to verify and optimize arrangement of wires, routes of return current, constants of “problem-solving” parts, or drive capability without waiting for evaluation of an actual board, reduce the need of reworking, and ultimately make a remarkable reduction in product development period.
Cooperative design of Packages and Motherboards
Development of coordinated design for a package and a board can optimize the buffer capability and signal pin assignment, and optimization of the power source ground pins can reduce the wiring area or the number of layers of a board. These measures ultimately allow us to propose board cost reduction. We can develop optimal design for high-speed wiring, such as DDR memory interfaces and high-speed serial interfaces, and power source systems. We have rich experience in coping with major ASIC/FPGA models.
Eye-pattern analysis of high-speed differential line
We can assess eye-pattern analysis of PCI Express Gen3, USB3.0, XAUI and others, and measure emphasis/equalizing at the design stage. We can implement solid wiring without transmission error.